Since AMD with Ryzen 4000 also sets the fastest processors in the notebook market, the eyes are directed on how Intel’s counter-looking. On an Architecture Day and present at the specialist conference Hot Chips HC32, the ChipGigant called first details, such as the upcoming 11. Core I Generation – Codename Tiger Lake – wants to counter dominant AMD processors: with optimizations at all fronts.
It’s about that Intel has developed a new transistor type called Superfin for its chospre’s 10-nanometer manufacturing process – with sophisticated marketing designations like "10nm+" So is a conclusion. Superfin transistors are used in new CPU nuclei (Codename Willow Cove), which bubble the ICE Lake Generation Sunny Cove Core. While the latter hardly reached more than 4 GHz, because the FINFET transistors used there do not tolerate the voltages required for higher clock rates, should now be around the 5 GHz in it. In addition, Intel promises a higher cycle even at low voltages and thus more performance with the same energy input.
Architecturally, Willow Cove brings significantly coarse caches: The L2 cache per core growth of 0.5 to 1.25 Mbytes and the L3 cache shared by several cores – with a four-core of 8 on 12 Mbytes. Intel did not want to answer for variants with more cores, but referred to the through-the-sized launch timetable: Concrete CPU models and their technical details should only be on 2. September be presented. On the Architecture Day, however, was also said that Tiger Lake has up to 24 Mbyte L3 cache – that sounds great about an OCTA Core. Whether such chips such as the Ryzen-4000 eight-cucore will give in the for flat notebook relevant 15-watt Abwarm budget or only in the 45-watt class for gaming-bolides and mobile workstations, is just as open as concrete statements performance.
Intel’s Willow Cove core for the 11. Core I generation is intended to offer high performance thanks to the new Superfin transistors than the previous 10 nanometer core Sunny Cove.
USB 4, Thunderbolt 4 and PCIe 4.0 for notebooks
The Thunderbolt Controller integrated at ICE LAKE was handled: Instead of Thunderbolt 3, Thunderbolt 4 is scheduled – and because this builds on USB 4, is of course the latter possibly possible. The storage controller controls how had DDR4-3200 or LPDDR4x-4267; For later in the lifecycle, LPDDR5 is already provided.
The PCIe Host Controller in the CPU later speaks PCIe 4.0. The exact number of Lanes did not want to betray Intel so far, but love only by looking for the concrete CPU model and its number of core. Delighted is four PCIe-4 at Quad-Corees.0-lanes for a rapid NVME SSD. So far, you found PCie 4.0 Only in desktop and server systems with AMD processors. Ryzen 4000 as a mobile displacement speaks in turn only PCIe 3.0 – According to AMD a conscious decision from electricity saving. Whether AMD will change with the successor Cezanne (Alias Ryzen 5000) remains to be seen – nor is there hardly secured information about CEZANNE away from on Zen 3 CPU cores, although the chip is already expected for early 2021.
Probably large conversion action with Tiger Lake concerns the integrated GPU: Intel let the brand new XE architecture debut. In Tiger Lake is a low-power variant (LP); As you are in comparison to previous IGPUs and AMD’s internal vega variants, art tests must show.
XE itself is intended as a chip family whose variants are tailored to different purposes. The LP version contained in Tiger Lake is trimmed to energy efficiency, but should also be used on dedicated entry-level graphics cards. For normal servers, the HP variant (high power) constructed from four identical chiplets is considered; For accelerators in super computers, there is the HPC dialect (High Performance Computing). Its first incarnation is called Ponte Vecchio and is intended for the supercomputer Aurora. According to Intel, Xe is so modular that you could omit the 3D units from a fine chip design for HPC variants to build a pure Ki accelerator.
Mid-range and high-end gamers should in turn after the latest member XE-HPG (High Performance Gaming) Lechzen, which incorporates additional functional units for ray-tracing effects. Spicy detail: Intel AMD and NVIDIA in the HPG chips even in the fact that the chips are commissioned externally and not come from the stands of the in-house Fabs. Intel’s timetable did not say anything; Thus, it was probably allowed to stand in 2021 an Intel graphics card in the store.
Speaking of new graphics cards: Already in short, Nvidia wants to sell the ampere generation available only as a100-chip as a successor of the two-year-old GPU family GeForce RTX 2000. Vimum details on the new GPU generation will be Nvidia on 1. September at a gross online event – on the hot chips only already known GPU details have been summarized.
On the other hand, at the third in the league, adviser rates are still announced. Although AMD had emphasized several times in the youngest past that the next high-end GPU developed under the name Big Navi should appear with ray-tracing support before the end of the year, but so far neither architecture details nor the launch timetable published.
However, AMD was currently having a resource problem: In the fall, the next consolation renewal is on, and both in the PlayStation 5 and Xbox Series X stuck individual processors that AMD developed in cooperation with Sony and Microsoft. The preparation of mass production is now just in the corona high phase for both consoles – since the finalization of the console-soCs prioritat could have received in front of the PC components.
After Sony had already entilled technical details about the PlayStation 5 in the spring, Microsoft presented the selected hardware design of the Scarlett SOC on the Hot Chips HC32. The eight Zen-2 cores acknowledge the mobile Ryzen-4000 CPUs with regard to the stripped caches and not the desktop implementation. Although the level expected, but Microsoft had previously spoken of server-class performance with reference to EPYC CPUs.
Microsoft promises that the CPU cores should run through 3.8 GHz (or 3.6 GHz in the SMT activated). The GPU, which occupies the coarse part of the flat, is intended to supply the 1.8 GHz throughout – console developers are no friends of fluctuating performance. Jerken questions about the TDP did not want to answer Microsoft.
For sufficient memory throughput, ten GDDR6 channels – High Bandwidth Memory (HBM) was discarded from cost. The internal SSD is two PCIe-4.0-lanes connected, which explains lower transfer rates compared to the PlayStation-5-SSD – and also the proprietary expansion shaft offers two PCIe-4.0-lanes. Four other lanes bind the chipset, which provides additional interfaces such as USB and SATA (for the Blu-ray drive).
The Microsoft’s own audio controller, however, is trimmed part of the Scarlett-SOC and for 3D audio: For floating-point calculations with simple accuracy, he will provide more throughput than all eight Zen-2 cores. In addition to the four Logan DSP cores known from the Xbox One family, there are now the real-time decoder "opus", the over 300 channels can be processed simultaneously. Of the surround profiles tailored to the user, as Sony’s Tempest Engine of the PS5 Chip should provide you, was not a speech. As there, however, there are hardware units that unpack the compressed data read from the SSD without access to the Zen cores, thus increasing the transfer rate.
In the Scarlett-Soco of the coming game console Xbox Series X, the GPU takes the coarse part of the one. The I / O units are distributed on three sides; The fourth is needed to feed sufficient power in the chip.
Last but not least, Microsoft said that despite the strategy of offering all in-house games for the PC, nothing more on the fact that the Xbox exploits the existing hardware console-typically efficiently efficient: operating system and drivers are much closer on the hardware oriented Windows PCS ALSO-SETTEAL HALL Layer (Hardware Abstraction Layer) has been completely eliminated. Also, Power developers at the DIRECTX API have accessed directly on some components.
This article comes from C’t 19/2020.