With the new graphics architecture XE, which is to deprive integrated processor graphics with the Tiger Lake processors, Intel has rough tarpaulin. Among other things, it should scalate from the low-power chip to the data center. The engineers had to convert the engineers to Xe a lot. For this purpose Intel has now submitted Intel on the Architecture-Day – and also a new, auber house made gaming variant and raytracing support in hardware. The first cards should come 2021.
From the IGP to the data center
With four XE variants, Intel wants to cover the complete market from the integrated graphics to the exascale accelerator for supercomputer. The XE entry is available in the integrated Tiger Lake graphics with the variant XE LP, the newly contaminated HPG version is used, which ranges via MID range to high-end graphics.
For KI applications in the data center, then Xe HP is intended and at the top of the portfolio superspire the HPC version, which as Ponte Vecchio is to be fired the Exaflops supercomputer Aurora. More than just conceivable is that each version offers special functions such as Tensor cores, high FP64 throughput for supercomputer or just raytracing hardware for supercomputer or just raytracing hardware for gamer.
The beginning shows XE LP, which is intended as an energy-efficient version for the integrated graphics and entry-level graphics cards DG1 and the server chips SG1. At today’s integrated graphics, XE LP is intended to pay back on paper with 96 execution units and 1536 floating-point operations per cycle – there are improvements by amendments to the architecture, such as the faster cache or simply the optimization of high clock rates.
A little more meaningful diagram, which Intel showed, indicates frequencies of 1.8 GHz for Xe LP – but at high voltage towards the current GEN11 graphic in ICE Lake processors, which only create around 1.1 GHz. Therefore, it is questionable whether such high bars will be found even with integrated graphics or not more in the dedicated graphics chips DG1 and SG1.
High Performance Gamer Aushausig
The newly contaminated variant "XE HPG" should combine the best of LP, HP and HPC: the efficiency of HPC’s arithmetic tasks, the scalability of the HP variant and the graphics efficiency of XE LP. Added to this – for the first time by Intel – hardware support for RayTracing on the slightly crude formulation "WITH HARDWARE DEDICATED RAYTRACING". Much more was not yet to be experienced, except the qualification, just this variant with external process technology, so in a chip postcarder like TSMC or Samsung, to produce. The fact that Intel has to go this step due to further delays in the own 7-nanometer technology, the company had to have the announcement of the quarterly numbers.
Intel XE: Four architectures, partly with external contract finishes.
360 Hz, 8K video and AV1 decoder
Also completely handled Intel the Media Engine of XE LP, so the display controller and video unit. Treaty supports the graphic over Displayport 1.4 and HDMI 2.0 A resolution of up to 8k, so 8192 × 4096 pixels. Maximum displays should be supported with 360 Hz and Adaptive Sync. XE LP relieves the processor in video playback of 8K content with 60 frames per second. For the first time, a hardware decoder for the license-free AV1 codec is also on board, the use of whose use is set for most coarse streaming services.
Intel XE LP: Upered Media Engine with AV1 Decoder, 8K60 Video, 360 Hz and Adaptive Sync.
In the data center variant XE HP, Intel also relies on a possible high transcoding performance – according to own information with a quality comparable to offline transcoders on the CPU. In a demo, first Xe silicum, which encoded 10 4k60 HEVC streams in parallel in real time.
XE scaling by tile
A demo of the scalability of the XE-HP architecture showed a single Tile one "Intel Xehp HD Graphics Neo", The under Linux (without more accurate distribution specification) reached around 10.6 Tflops FP32 computer throughput, ie 10.6 trillion floating communication steps per second. This is about the performance level of a fast Radeon RX 5700 XT. Then the Intel engineers switched two and finally four tiles, ie chip instances, and achieved a nearly perfect scaling of computing power in the synthetic benchmark. The art is, of course, this also for more complex calculations or for real graphics load.
Scaling Demo: A single HP-XE chip already creates 10.5 tflops and lets you pair four times.
The XE-HP chip ran with 1.3 GHz and loudly had the log 2048 Compute Units – highly probably 4096 FP32-FMA per stroke.