Amd rally with processors with “potted” cache chip

AMD rally with processors with'aufgestapeltem' cache-chip an'aufgestapeltem' cache-chip an

AMD-CEO DR. LISA su Krundiger in its keynote presentation on the Computex virtual fair an innovation of chip-housing technology: 3D V-Cache. Already so far AMD let the EPYC processors for servers and the Ryzen processors compose for desktop PCs from multiple chiplets. These sit side by side on a common the carrier.

At the same time, AMD also wants to stack these two, so the vertical as a third dimension remained: on each Core Complex the (CCD) the application-ready TSMC sets an additional SRAM-the 36 square millimeter Flat. It extends the internal, 32 Mbyte L3 cache of the CCD by 64 Mbytes to a total of 96 MB.

AMD rally with processors with'aufgestapeltem' cache-chip an'aufgestapeltem' cache-chip an

On the left CCD chiplet this processed prototype of a Ryzen 9 5900x you recognize the 3D V-Cache-the.

LISA Su showed the pattern of a prototype of a Ryzen 9 5900x with 3D V-cache, where both the warm distribution plate (Integrated Heat Spreader, IHS) and additional silicon plates were removed from the left of the two CCDs. As a result, the square SRAM-which is visible with 6 mm edge length.

SU stressed that in the finished series product, the stacked SRAM-which does not recognize with Blobem Eye, because right and left are applied adjacent silicon platches: these serve of mechanical strength and provide for alarm line from the lower CCD to the IHS.

The finished processor also has to have the same high as the versions without 3D V-cache, so that the contact prere of the cooler fits. Therefore, the stacked chiplets are tuned accordingly.

192 MBYTE L3 cache

The still hypothetical Ryzen 9 5900x with two eight core CCDs (with six active cores each) containing 32 MB of L3 cache each comes with two additional 64 MBS-SRAMs on a total of 192 Mbyte L3 cache. Compared to the previous version of the Ryzen 9 5900X with "only" 64 MBT L3 cache is supposed to bring the giant cache on average 15 percent higher refresh rates for PC games with Full HD resolution.

Lisa Su did not go to other CPU versions with 3D V-cache. In recent months, however, there were speculations about a server processor with the alleged code name "Milan-X" (The EPYC 7003 is called "Milan") To have additional HBM2 memory chips. For 2022 plans competitor Intel several processors with the in-house Foveros stacking technology.

Stacked without lot

The AMD boss emphasized that the stacking technique of TSMC extremely high contact densities possible and does not use solubries. Instead, the chips with direct copper compounds sit directly. In addition, Through-Silicon VIIs (TSVs) are used, ie vertical compounds through one therethrough.

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